This invention relates to a microprogram control system for use in a data processor.
In ordinary data processors, control operations for the execution of software instructions are performed in accordance with command signals issuing from a control unit composed of logic circuits. As a result, the control unit is so complicated that it is difficult to obtain desired alterations in the processor operations. On the other hand, microprogram-controlled data processors which have been developed recently control the execution of software instructions by storing a plurality of microinstructions in a dedicated memory, sequentially reading these microinstructions out of the memory, and decoding them. The processors of this type have an advantage that the aforementioned alterations in processor operations can be easily attained by simply rewriting the microinstructions involved. Elevation of the operating speed in such processors requires high speed operations in the dedicated memory. Dedicated memories operable at high speeds are, however, highly expensive.
Incidentally, high speed operations are demanded for the execution of general software instructions. There are, nevertheless, software instructions such as ones directed to exceptional processings which may be processed at relatively low speeds without adversely affecting the performance of the processor operations. Heretofore, even the latter software instructions have been executed by using a plurality of microinstructions stored in a high-speed memory, thus preventing economic use of the high-speed memory. As a solution to this problem, there has been proposed a system in which a plurality of microinstructions for the execution of software instructions deserving low-speed processings are stored in an ordinary main memory, a necessary microinstruction is read out of the main memory each time a request for relevant processing occurs, and the read out microinstruction is overlaid or overwritten on a presently unnecessary microinstruction stored in a memory dedicated to controlling the execution of software instructions. For further details of the construction of this system, reference is made to the specification of U.S. Pat. No. 3,478,322. To be more specific, in the system disclosed in this patent specification, a microinstruction issued from a main memory (denoted by reference numeral 36 in FIG. 1A) is delivered to ECCS1 and ECCS2 via a computer I/O channel 6, a channel to channel adapter 40, and an ECCS I/O channel 5.
This system is not free from the disadvantage that design alterations are not easily accomplished, because the control operations involved are performed through the medium of a control unit formed by complicated logic circuits as mentioned above.